Development Skills |
High performance computing
- Multi-threaded and distributed system architecture;
Languages and systems
- C, C++, Java, Python, Scheme, Fortran, Assembly;
Networking
- Internet protocol V4 and V6;
System architectures, Compiler technology
- IA32, IA64, PPC, ARM, SPARC, MC68000;
Development
- Git, Subversion, CVS, Clearcase.
Management
- International multi-sites project management;
|
Professional experiences |
Quantic Dream (Paris, France - Since May 2022)Low level engine senior contributor. Responsible for the development and implementation of high-performances mathematical libraries in C++. The mathematical chain is a key element of a gaming experience which interacts with numerous engine, inclusing the physical and rendering engines. Ethernix (Lorient, France - Since Dec 2019)Founder of the Ethernix company. Ethernix is a long term project targeting the deployment of the “Constellation Computing” technology developed from the ground up. The constellation integrates in a single platform several computing models, including gpu compute shaders, browser web assembly and newer quantum computing virtual engine. The platform is currently under test and can be visited at Ethernix Constellation . Blade Group (Paris, France - Dec 2015, Dec 2019)Fellow - Head of the software research lab. Original developer of the Shadow product cloud server with an emphasis on low latency, high-quality, high-speed acquisition and encoding facility. Other duties include managing the research lab and following interns from various schools (Telecom Paris, École Polytechnique, Université Paris 6). CACIB (Paris La Défense, France - May 2015, Dec 2015)Consultant in the e-trading department for the development and optimization of the feed-handler components of the new e-trading platform. A feed-handler is a critical component that collect financial instrument data and distribute them on the internal bus for further processing by pricing components which are part of an automated tool chain within a financial desk. Silkan (Montréal, QC - Canada - Sep 2012, Oct 2014)Lead architect. Lead architect for a high-performance software modeling project centered around a multithreaded and distributed execution core with a strong emphasis on complex numerical computation. Silkan (Meudon - France - Apr 2010, Sep 2012)Senior software expert. Silkan is a French company based in Meudon, France. Silkan is specialized in the design of high performances computing platforms. Most of the projects are addressing the very demanding EDA sector by developing and deploying an advanced algebraic library. ESILV (Paris, France, Sep 2007, Jun 2010)Director of the information engineering department at ESILV. ESILV is an engineering school, located in the Léonard de Vinci complex in Paris La Défense. The information engineering department is responsible for the graduation of engineers specially trained in the field of computer sciences. Virtutech (San Jose, Ca - Jan 2005, Nov 2005)Senior software manager for Virtutech, Inc located in San Jose, Ca. The primary duties are to pilot the device modeling operations in the US in relation with the Stockholm research center. Principal duties includes device and machine modeling for a broad range of systems with an emphasis on the embedded kernel simulation or with the full operating system execution. IRISA (Rennes, France - Jan 2002, Dec 2004)PhD student of André Seznec. The PhD thesis title is "out-of-order execution with predicate ISA". In order to attack the problems associated with the out-of-order execution of predicated ISA, a complete simulation infrastructure based on the Itanium IA64 ISA has been implemented. Cadence Design Systems (San Jose, Ca - Sep 1998, Sep 2001)Senior member of the consulting staff. Member of the PKS team of the Ambit group of Cadence. The objective was to deliver a new CAD framework which handle multi-million gates design with first time working timing/routing silicon. Aristo Technology (Cupertino, Ca - Feb 1997, Sep 1998)Principal engineer. Aristo Technology, Inc. Join the company on February 1997. Responsible for the project integration. The project is focusing on the new System-on-a-Chip (SOC) paradigm. Develop a run-time dynamic application manager. Compass Design Automation (San Jose, Ca - Jun 1995, Feb 1997)Worldwide application manager for the front-end tools. With a small team of corporate engineers, responsible of the Compass synthesis solution, including HDL floorplanning and its link with the floorplanner. Compass Design Automation (Paris, France - Mar 1993, Jun 1995)Eastern countries special operations. Special project engineer working on long term projects with various Compass customers. Compass Design Automation (Nice, France - Mar 1991, Mar 1993)Special projects ASIC design engineer. The main project included a complete library re-design with 300 standard cells, their adaptation to a low-voltage operation. VLSI Technology (Nice, France - Jun 1989, Mar 1991)Design engineer. Develop and characterized a 20 MHz version of the Z80 in the VLSI 1.0µm technology. |
Business experiences |
Ethernix (Lorient, France, since Nov 2005)Founder of the Ethernix company. Ethernix develops on demand software solution in the field of high-performance, parallel and distributed computing. Currently working on the “constellation computing” project visible at Ethernix Constellation . |
Academic experiences |
ESEO (Paris, Sep 2007,2010 2015,2017)Lecturer in computer sciences at ESEO Paris for undergraduate students. ESILV (Paris, La Défense - Sep 2007, Jun 2010)Director of the information engineering departement. ESEO (Angers - Since 2004)Special lecturer for an introduction to the software complexity. The introduction covers the fundamental aspects of the information theory as well as the language theory complexity. ESEO (Angers - 2002, 2004)Professor at Engineering school, ESEO located in Angers. The course, with 130 students, covers the fundamentals of front-end compiler design. A special emphasis on the automaton theory is made during the course. ESIEE (Paris - 1993, 1995Professor at Engineering school, ESIEE located in Marne La Vallée, near Paris. The course covered the fundamental of parallel architecture with an emphasis on superscalar scheduling and systolic implementation. |
Education |
- PhD in Computer Sciences from Rennes University, France
|
copyright © 2005-2024 Amaury Darsch